LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
LH540235/45
TIMING DIAGRAMS (cont’d)
Enhanced Operating Mode Timing Diagram
A
WCLK
tDS
D0 - D17
DATA WRITE 1
tENS
tENH
WEN
RCLK
tSKEW2(1)
B
tPAES
PAE
2048 x 18/4096 x 18 Synchronous FIFOs
C
tDS
DATA WRITE 2
tENH
tENS
tSKEW2(1)
tPAES
tPAES
REN
OE
LOW
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a
rising RCLK edge for PAE to change predictably during the current
clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then it is not guaranteed
that PAE will change state until the next following RCLK edge.
2. PAE offset = q. Also, number of data words written into FIFO already = q.
3. The internal state of the FIFO:
At A , q+1 words.
At B , q words.
At C , q+1 words again.
DATA READ
Figure 15. Programmable-Almost-Empty Flag Timing,
When Synchronous (Enhanced Operating Mode)
540235-23
28
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