LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
WCLK
D0 - D17
WEN
RCLK
EF
tDS
DATA WRITE 1
tENS
tENH
tFRL(2)
tSKEW2(1)
tREF
tDS
DATA WRITE 2
tENH
tENS
tFRL(2)
tSKEW2(1)
tREF
tREF
tREF
EF2
REN
OE
LOW
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a
rising RCLK edge for EF to change predictably during the current
clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then it is not guaranteed
that EF will change state until the next following RCLK edge.
2. tFRL (First-Read Latency) is the minimum time between a rising WCLK
edge and a rising RCLK edge to assure a correct readout of the first data
word D0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2.
If tFRL is not met, D0 may be available either at tCLK + tSKEW2, or after
one more clock cycle delay at 2 tCLK + tSKEW2. The First-Read Latency
timing restrictions apply only when the FIFO has been empty (EF = LOW).
3. EF may be used to determine when the first data word D0 may be read.
D0 always is available on the next cycle after EF has gone HIGH.
BOLD ITALIC = Enhanced Operating Mode.
Figure 11. Empty-Flag Timing
LH540235/45
tREF
540235-10
25
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