LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
Enhanced Operating Mode Timing Diagram
WCLK
NO WRITE
tSKEW1(1)
D0 - D17
NO WRITE
B
tDS
DATA WRITE
tPAFS
tSKEW1(1)
tDS
DATA WRITE
tPAFS
tPAFS
PAF
WEN
RCLK
A
tENS
tENH
C
tENS
tENH
REN
LOW
OE
tA
tA
Q0 - Q17
DATA IN
OUTPUT REGISTER
DATA READ
NEXT
DATA READ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a
rising WCLK edge for PAF to change predictably during the current
clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW1, then it is not guaranteed
that PAF will change state until the next following WCLK edge.
2. PAF offset = p. Number of data words written into FIFO already = 2047 - p
for the LH540235 and 4095 - p for the LH540245.
3. The internal state of the FIFO:
At A , 2047 - p words in FIFO for LH540235 and 4095 - p words in FIFO for LH540245.
At B , 2048 - p words in FIFO for LH540235 and 4096 - p words in FIFO for LH540245.
At C , again 2047 - p words in FIFO for LH540235 and 4095 - p words in FIFO for LH540245.
Figure 17. Programmable-Almost-Full-Flag Timing,
When Synchronous (Enhanced Operating Mode)
540235-24
30
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