LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
RCLK
tCLKH
tCLK
tCLKL
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 - Q17
tOLZ
tOE
VALID DATA OUT
tOHZ
OE
tSKEW2 (1)
WCLK
WEN
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a
rising RCLK edge for EF to change predictably during the current
clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then it is not guaranteed
that EF will change state until the next following RCLK edge.
Figure 8. Synchronous Read Operation
540235-7
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