LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
WCLK
D0 - D17
NO WRITE
NO WRITE
tSKEW11
tDS
tWFF
DATA WRITE
tWFF
tSKEW11
tDS
DATA WRITE
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
OE
Q0 - Q17
LOW
tA
DATA IN
OUTPUT REGISTER
tA
DATA READ
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a
rising WCLK edge for FF to change predictably during the current
clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW1, then it is not guaranteed
that FF will change state until the next following WCLK edge.
Figure 10. Full-Flag Timing
NEXT
DATA READ
540235-9
24
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