LHF16KA7 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF16KA7' PDF : 53 Pages View PDF
SHARP
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LHFlGKA7
10
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Table 4. Command Definitions(l”)
Bus Cycles Notes
First Bus Cycle
Second Bus Cycle
Command
Req’d
Oper(‘) 1Add&*) 1 Data13) Ope#) 1Addr(*) 1 Data13)
Read Array/Reset
1
Write ( X 1 FFH
22
4
Write
X
90H Read
IA
‘D II
22
Write
X
98H Read
QA
C
2
W_.r.it.e_- X
70H Read
X
T
Write
X
2
5
Write
BA
2
Write
X
2
55
Write
WA
4lternate Word/Byte Write
SetupWrite
2
596 Write WA
10H Write WA
WD
Multi Word/Byte Write
Setup/Confirm
24
9
Write WA
E8H Write
WA
N-l
Block Erase and (Multi)
Word/byte Write Suspend
1
5 Write
X
BOH
Confirm and Block Erase and
(Multi) Word/byte Write Resume
1
5
Write
X
DOH
Block Lock-Bit Set Setup/Confirm
2
7
Write
BA
60H Write
BA
OlH
Block Lock-Bit Reset
Setup/Confirm
2
8 Write
X
60H Write
X
DOH
STS Configuration
Level-Mode for Erase and Write
2
Write
X
B8H Write
X
OOH
(RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
2
Write
X
B8H Write
X
OlH
STS Configuration
Pulse-Mode for Write
2
Write
X
B8H Write
X
02H
STS Configuration
Pulse-Mode for Erase and Write
2
Write
X
B8H Write
X
03H
NOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
2. X=Any valid address within the device.
IA=ldentifiep Code Address: see Figure 4.
QA=Quety Offset Address.
BA=Address within the. block being erased or locked.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 14 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.
4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts
to issue a block erase or (multi) word/byte write to a locked block while RP# is VI,.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. A block lock-bit can be set while WP# is VI,.
8. WP# must be at VI, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block
lock-bits.
9. Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm
command ‘DOH’.
10. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 1.9
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