LHF16KA7 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

MFG CO.

LHF16KA7

Flash Memory 16M (2MB × 8/1MB × 16)

Sharp Electronics 

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4.1 Read Array Command

LHF16KA7

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4.3 Read Status Register Command

Upon initial device power-up and after exit from deep

power-down mode, the device defaults to read array

mode. This operation is also initiated by writing the

Read Array command. The device remains enabled

for reads until another command is written. Once the

internal WSM has started a block erase, full chip

erase, (multi) word/byte write or block lock-bit

configuration, the device will not recognize the Read

Array command until the WSM completes its

operation unless the WSM is suspended via an Erase

Suspend and (Multi) Word/byte Write Suspend

command. The Read Array command functions

independently of the VP,, voltage and RP# must be

Vi,*

4.2 F&ad Identifier Codes Command

The identifier code operation is initiated by writing the

Read Identifier Codes command. Following the

command write, read cycles from addresses shown in

Figure 4 retrieve the manufacturer, device, block lock

configuration and block erase status (see Table 5 for

identifier code values). To terminate the operation,

write another valid command. Like the Read Array

command, the Read Identifier Codes command

functions independently of the V,, voltage and RP#

must be V,,. Following the Read Identifier Codes

command, the following information can be read:

Table 5. Identifier Codes

Code

Address

Data

Manufacture Code

./

Device Code

00000

00001

BO

00002

00003

Block Status Code

x0004(’ )

x0005(‘) ~

*Block is Unlocked

DC&,=0

l Block is Locked

DQc= 1

*Last erase operation

1

completed successfully

/ DQ,=O 1

@Lasterase operation did

not completed successfully

DQ,=l

OReserved for Future Use

DQyw7

NOTE:

1. X selects the specific block status code to be

read. See Figure 4 for the device identifier code

memory map.

The statusregister may be read to determine when i

block erase, full chip erase, (multi) word/byte write OI

block lock-bit configuration is complete and whethei

the operation completed successfully(see Table 14)

It may be read at any time by writing the Read Statu:

Register command. After writing this command, al

subsequent read operations output data from the

status register until another valid command is written

The status register contents are latched on the fallins

edge of OE# or CE#(Either CE,# or CE,#)

whichever occurs. OE# or CE#(Either CE,# or CE,#:

must toggle to ‘Jr, before further reads to update the

status register latch. The Read Status Register

command functions independently of the V,, voltage

RP# must be VI,.

The extended status register may be read tc

determine multi word/byte write availability(see Table

14.1). The extended status register may be read a

any time by writing the Multi Word/Byte Write

command. After writing this command, all subsequen

read operations output data from the extended statuz

register, until another valid command is written. Mult

Word/Byte Write command must be re-issued tc

update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.l are

set to “1”s by the WSM and can only be reset by the

Clear Status Register command. These bits indicate

various failure conditions (see Table 14). By allowins

system software to reset these bits, severa

operations (such as cumulatively erasing or lockinc

multiple blocks or writing several bytes in sequence:

may be performed. The status register may be pollee

to determine if an error occurs during the sequence.

To clear the status register, the Clear Status Register

command (50H) is written. It functions independently

of the applied V,, Voltage. RP# must be VI,. This

command is not functional during block erase, ful

chip erase, (multi) word/byte write block lock-bii

configuration, block erase suspend or (multi:

word/byte write suspend modes.

Rev. 1.9

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