LHF16KA7 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF16KA7' PDF : 53 Pages View PDF
SHARP
_ - _-
LHF16KA7
16
1
4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
SR.7.
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for “1”s that
do not successfully write to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable word/byte writes can only occur when
Vcc=Vcc,,2 and VPP=VPPH112,3.In the absence of
this high voltage, memory contents are protected
against word/byte writes. If word/byte write is
attempted while V+V,,,,, status register bits SR.3
and SR.4 will be set to “1”. Successful word/byte
write requires that the corresponding block lock-bit be
cleared or, if set, that WP#=V,,. If word/byte write is
attempted when the corresponding block lock-bit is
set and WP#=V,,, SR.1 and SR.4 will be set to “1”.
Word/byte write operations with V,,<WP#<V,,
produce spurious results and ,should not be
attempted. ”
4.9 Multi Word/Byte Write Command
Multi word/byte write is executed by at least four-
ycle or up to 35cycle command sequence. Up to
32 bytes in x8 mode (16 words in xl6 mode) can be
oaded into the buffer and written to the Flash Array.
=irst, multi word/byte write setup (E8H) is written with
:he write address. At this point, the device
automatically outputs extended status register data
:XSR) when read (see Figure 8, 9). If extended
status register bit XSR.7 is 0, no Multi Word/Byte
Nrite command is available and multi word/byte write
setup which just has been written is ignored. To retry,
continue monitoring XSR.7 by writing multi word/byte
write setup with write address until XSR.7 transitions
to 1. When XSR.7 transitions to 1, the device is ready
for loading the data to the buffer. A word/byte count
(N)-1 is written with write address. After writing a
word/byte count(N)-1, the device automatically turns
back to output status register data. The word/byte
count (N)-1 must be less than or equal to 1FH in x8
mode (OFH in x16 mode). On the next write, device
start address is written with buffer data. Subsequen
writes provide additional device address and data
depending on the count. All subsequent addres:
must lie within the start address plus the count. Afte
the final buffer data is written, write confirm (DOH
must be written. This initiates WSM to begin copyin!
the buffer data to the Flash Array. An invalid Mull
Word/Byte Write command sequence will result iI
both status register bits SR.4 and SR.5 being set tc
“1”. For additional multi word/byte write, write anothe
multi word/byte write setup and check XSR.7. Tht
Multi Word/Byte Write command can be queuec
while WSM is busy as long as XSR.7 indicates “1”
because LH28F160S3HT-LlOA has two buffers. If ar
error occurs while writing, the device will stop writins
and flush next multi word/byte write command loader
in multi word/byte write command. Status register bi
SR.4 will be set to “1”. No multi word/byte writ6
command is available if either SR.4 or SR.5 are se
to “1”. SR.4 and SR.5 should be cleared before
issuing multi word/byte write command. If a mult
word/byte write command is attempted past an erase
block boundary, the device will write the data to Flast
Array up. to an erase block boundary and then stag
writing. Status register bits SR.4 and SR.5 will be se
to “1 ‘I.
Reliable multi byte writes can only occur wher
Vcc=Vcc1,2 and VPP=VP~H11213.In the absence o
this high voltage, memory contents are protectec
against multi word/byte writes. If multi word/byte write
is attempted while V+V,,,,,
status register bits
SR.3 and SR.4 will be set to “1”. Successful muIt,
word/byte write requires that the corresponding block
lock-bit be cleared or, if set, that WP#=V,,. If muIt,
byte write is attempted when the corresponding block
lock-bit is set and WP#=V,,, SR.l and SR.4 will be
set to “1 ‘I.
Rev. 1.9
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