LHF16KA7 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF16KA7' PDF : 53 Pages View PDF
SHARP
LHF16KA7
-- -
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(‘)
I
Sym. 1
v ,,=2.7\1-3.6\
Versions@)
Parameter
~-40°C to +85â€C
1 LH28F160S3H-L120 1
I
( Notes 1 Min. ( Max.
Unit !
h
WE# Hold from CE# Hiah
..-
tFWF, 8 CE# Pulse Widt :h High
25
ns
tfq+n, CE# High to STS Going Low
100
ns
fFHG, Write Recovery before Read
0
ns
Vpp Hold from Valid SRD, STS High Z
24
0
ns
WP# VIH Hold from Valid SRD, STS High Z
2,4
0
ns
NOTE:
See 3.3V Vco Alternative CE#-Controlled Writes for nc)tes 1 through 5.
( Write Cycle Time
clFl 1RP# High Recovery to CE# Going Low
I 100
I
2
1
tâ€pFw
tJJFH
$-)“FH
Vpp Setup to CE# Goi
Address Setup to CE# Going High
Datd Setup to CE# Going High
11tFwax I Address Hold from CE# High
3
50
tFClr,, Write Recovery before Read
0
ns
hWl
Vpp Hold from Valid SRD, STS High Z
24
0
ns
tnVSl
WP# V,, , Hold from Valid SRD, STS High Z
2,4
0
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. V,, should be held at V,,,,,z,, until determination of block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
Rev. 1.9
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