sharp
LHF32KZ5
47
Sym.
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
Versions
VCC=5V±0.25V(5)
Parameter
Notes Min.
Max.
VCC=5V±0.5V(6)
Min.
Max.
Unit
tAVAV Write Cycle Time
70
80
ns
tPHEL RP# High Recovery to BE# Going Low
2
1
1
µs
tWLEL WE# Setup to BE# Going Low
0
0
ns
tELEH BE# Pulse Width
50
50
ns
tSHEH WP# VIH Setup to BE# Going High
2
100
100
ns
tVPEH VPP Setup to BE# Going High
2
100
100
ns
tAVEH Address Setup to BE# Going High
3
40
40
ns
tDVEH Data Setup to BE# Going High
3
40
40
ns
tEHDX Data Hold from BE# High
5
5
ns
tEHAX Address Hold from BE# High
5
5
ns
tEHWH WE# Hold from BE# High
0
0
ns
tEHEL BE# Pulse Width High
25
25
ns
tEHRL BE# High to STS Going Low
90
90
ns
tEHGL Write Recovery before Read
0
0
ns
tQVVL VPP Hold from Valid SRD, STS High Z 2,4
0
0
ns
tQVSL WP# VIH Hold from Valid SRD, STS
High Z
2,4
0
0
ns
NOTES:
1. In systems where BE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the BE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, bank erase, (multi) word/byte write or block lock-bit
configuration.
4. VPP should be held at VPPH1/2/3 until determination of block erase, bank erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5=0).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.