LPC1769 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'LPC1769' PDF : 79 Pages View PDF
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
tf
70 %
SDA 30 %
SCL
tf
70 %
30 %
tSU;DAT
70 %
30 %
tHD;DAT
70 %
30 %
S
1 / fSCL
70 %
30 %
tLOW
tHIGH
tVD;DAT
70 %
30 %
Fig 17. I2C-bus pins clock timing
002aaf425
11.6 I2S-bus interface
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See
Table 2.
Table 14. Dynamic characteristics: I2S-bus interface pins
Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
common to input and output
tr
rise time
tf
fall time
tWH
pulse width HIGH
[1] -
-
[1] -
-
on pins I2STX_CLK and [1] 0.495 × Tcy(clk) -
I2SRX_CLK
tWL
pulse width LOW
on pins I2STX_CLK and [1] -
-
I2SRX_CLK
Max
Unit
35
ns
35
ns
-
-
0.505 × Tcy(clk) ns
output
tv(Q)
data output valid time
on pin I2STX_SDA
on pin I2STX_WS
[1] -
[1] -
-
30
ns
-
30
ns
input
tsu(D)
data input set-up time
on pin I2SRX_SDA
[1] 3.5
-
-
ns
th(D)
data input hold time
on pin I2SRX_SDA
[1] 4.0
-
-
ns
[1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK⁄4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK
signal in the I2S-bus specification.
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
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