LPC1769 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'LPC1769' PDF : 79 Pages View PDF
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
11.9 SPI
Table 17. Dynamic characteristics of SPI pins
Tamb = −40 °C to +85 °C.
Symbol Parameter
Min
Tcy(PCLK) PCLK cycle time
TSPICYC
SPI cycle time
tSPICLKH SPICLK HIGH time
tSPICLKL
SPICLK LOW time
SPI master
10
[1] 79.6
0.485 × TSPICYC
tSPIDSU
SPI data set-up time
[2] 0
tSPIDH
SPI data hold time
[2] 2 × Tcy(PCLK) − 5
tSPIQV
SPI data output valid time [2] 2 × Tcy(PCLK) + 30
tSPIOH
SPI output data hold time [2] 2 × Tcy(PCLK) + 5
SPI slave
tSPIDSU
tSPIDH
tSPIQV
tSPIOH
SPI data set-up time
[2] 0
SPI data hold time
[2] 2 × Tcy(PCLK) + 5
SPI data output valid time [2] 2 × Tcy(PCLK) + 35
SPI output data hold time [2] 2 × Tcy(PCLK) + 15
Typ Max
Unit
--
ns
--
ns
--
ns
-
0.515 × TSPICYC ns
--
ns
--
ns
--
ns
--
ns
--
ns
--
ns
--
ns
--
ns
[1] TSPICYC = (Tcy(PCLK) × n) ± 0.5 %, n is the SPI clock divider value (n ≥ 8); PCLK is derived from the
processor clock CCLK.
[2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
SCK (CPOL = 0)
TSPICYC
tSPICLKH tSPICLKL
SCK (CPOL = 1)
MOSI
MISO
tSPIQV
DATA VALID
DATA VALID
tSPIDSU
tSPIDH
DATA VALID
DATA VALID
Fig 22. SPI master timing (CPHA = 1)
tSPIOH
002aad986
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
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