NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
19. Revision history
Table 37. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
LPC178X_7X v.5.5
Modifications:
20160426
Product data sheet
-
LPC178X_7X v.5.4
• Updated Table 29 “Dynamic characteristics: LCD”: td(QV) max value is 9 ns for accuracy;
was 12 ns.
LPC178X_7X v.5.4
Modifications:
20160321
Product data sheet
CIN 201603016I LPC178X_7X v.5.3
• Added Table 18 “Dynamic characteristics: Dynamic external memory interface, read
strategy bits (RD bits) = 00” for 10 pF load.
• Updated Table 19 “Dynamic characteristics: Dynamic external memory interface, read
strategy bits (RD bits) = 00” for 30 pF load.
• Added Table 20 “Dynamic characteristics: Dynamic external memory interface, read
strategy bits (RD bits) = 01” for 10 pF load.
• Updated Table 21 “Dynamic characteristics: Dynamic external memory interface, read
strategy bits (RD bits) = 01” for 30 pF load.
• Updated Table 22 “Dynamic characteristics: Dynamic external memory interface
programmable clock delays (CMDDLY, FBCLKDLY, CLKOUT0DLY and CLKOUT1DLY)”.
• Updated Figure 19 “Dynamic external memory interface signal timing”.
LPC178X_7X v.5.3
Modifications:
20151015
Product data sheet
-
LPC178X_7X v.5.2
• Corrected max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) +
6.3 ns. Was: 3*Tcy(PCLK) + 2.5 ns. See Table 26 “Dynamic characteristics: SSP pins in SPI
mode”.
LPC178X_7X v.5.2
Modifications:
20150814
Product data sheet
-
LPC178X_7X v.5.1
• Updated max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) +
2.5 ns. See Table 24 “Dynamic characteristics: SSP pins in SPI mode”.
• Added a column for GPIO pins and device order part number to the ordering options table.
See Table 2 “LPC178x/7x ordering options”.
LPC178X_7X v.5.1
Modifications:
20140501
Product data sheet
-
LPC178X_7X v.5
• Updated parameter tsu(D) in Table 18 “Dynamic characteristics: Dynamic external memory
interface, read strategy bits (RD bits) = 00”: Minimum value changed to (FBCLKDLY + 1)
0.25 + 0.3. Maximum value removed.
• Removed max value from parameter th(D) in Table 17.
• Removed min value from parameter tdeact in Table 17.
• Specified ADC conversion rate in burst mode in Table 29 “12-bit ADC characteristics”.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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