LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 37. Revision history …continued
Document ID
Release date Data sheet status
Change notice Supersedes
LPC178X_7X v.5
20140501
Product data sheet
-
Modifications:
• Removed overbar from NMI.
• Table 3:
LPC178X_7X v.4.1
– Added minimum reset pulse width of 50 ns to RESET pin.
– Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC).
– Added boundary scan information to description for RESET pin.
– Updated pin description of STCLK.
• Table 13: Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
• Table 23: Removed reference to RESET pin from Table note 1.
• Table 24:
– Removed Tcy(PCLK) spec; already given by the maximum chip frequency.
– Changed min clock cycle time for SSP slave from 120 to 100.
– Updated Table note 1 and Table note 3.
• Table 29: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
• Section 7.21.1 “Features”: Changed max speed for SSP master from 60 to 33.
• and added typical specs Table 17, Table 18, Table 19.
• SOT570-2 obsolete; replaced with SOT570-3.
• Table 17:
– Updated EMC timing specs to CL = 30 pF.
– Added typical specs.
– Table note 3: Changed Tcy(clk) = 1/CCLK to Tcy(clk) = 1/EMC_CLK.
• Table 18:
– Updated EMC timing specs to CL = 30 pF
– Added typical specs.
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
• Table 19:
– Updated EMC timing specs to CL = 30 pF
– Added typical specs.
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
120 of 126
Share Link: 