LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
11.6 SSP interface
Table 26. Dynamic characteristics: SSP pins in SPI mode
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter
Conditions
Min
Max
Unit
SSP master
Tcy(clk)
clock cycle time
full-duplex
[1] 30
-
ns
mode
when only
30
-
ns
transmitting
tDS
data set-up time
in SPI mode [2] 14.8
-
ns
tDH
data hold time
in SPI mode [2] 2
-
ns
tv(Q)
data output valid
in SPI mode [2] -
6.3
ns
time
th(Q)
data output hold time in SPI mode [2] 2.4
-
ns
SSP slave
Tcy(clk)
tDS
tDH
tv(Q)
clock cycle time
data set-up time
data hold time
data output valid
time
in SPI mode
in SPI mode
in SPI mode
[3]
[3][4]
[3][4]
[3][4]
100
14.8
2
-
-
ns
-
ns
-
ns
3*Tcy(PCLK) + 6.3 ns
th(Q)
data output hold time in SPI mode [3][4] 2.4
-
ns
[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited
by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster
than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain.
5The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the
SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register),
and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V.
[3] Tcy(clk) = 12 Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate.
[4] Tamb = 25 C; VDD(3V3) = 3.3 V.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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