LPC2131 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
LPC2131
Philips Electronics
'LPC2131' PDF : 41 Pages View PDF
Philips Semiconductors
LPC2131/2132/2134/2136/2138
Single-chip 16/32-bit microcontrollers
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.21 System control
6.21.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz
and with external oscillator up to 50 MHz. The oscillator output frequency is called fosc and
the ARM processor clock frequency is referred to as CCLK for purposes of rate equations,
etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to
Section 6.21.2 “PLL” for additional information.
6.21.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 µs.
6.21.3 Reset and wake-up timer
Reset has two sources on the LPC2131/2132/2134/2136/2138: the RESET pin and
watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter.
Assertion of chip reset by any source starts the wake-up timer (see wake-up timer
description below), causing the internal chip reset to remain asserted until the external
reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and
the on-chip Flash controller has completed its initialization.
9397 750 14868
Preliminary data sheet
Rev. 02 — 15 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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