LPC2131 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
LPC2131
Philips Electronics
'LPC2131' PDF : 41 Pages View PDF
Philips Semiconductors
LPC2131/2132/2134/2136/2138
Single-chip 16/32-bit microcontrollers
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.21.4 Brown-out detector
The LPC2131/2132/2134/2136/2138 include 2-stage monitoring of the voltage on the VDD
pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt; if not, software can monitor
the signal by reading dedicated register.
The second stage of low-voltage detection asserts reset to inactivate the
LPC2131/2132/2134/2136/2138 when the voltage on the VDD pins falls below 2.6 V. This
reset prevents alteration of the Flash as operation of the various elements of the chip
would otherwise become unreliable due to low voltage. The BOD circuit maintains this
reset down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
6.21.5 Code security
This feature of the LPC2131/2132/2134/2136/2138 allow an application to control whether
it can be debugged or protected from observation.
If after reset on-chip boot-loader detects a valid checksum in Flash and reads
0x87654321 from address 0x1FC in Flash, debugging will be disabled and thus the code
in Flash will be protected from observation. Once debugging is disabled, it can be enabled
only by performing a full chip erase using the ISP.
6.21.6 External interrupt inputs
The LPC2131/2132/2134/2136/2138 include up to nine edge or level sensitive External
Interrupt Inputs as selectable pin functions. When the pins are combined, external events
can be processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
9397 750 14868
Preliminary data sheet
Rev. 02 — 15 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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