LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
Line Control Register (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start
LSB Data 5-8 bits MSB Parity
Figure 1 - Serial Data
Stop
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of
bits 0 and 1 is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
0
0
1
1
BIT 0
0
1
0
1
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following
table summarizes the information.
BIT 2
0
1
1
1
1
WORD LENGTH
--
5 bits
6 bits
7 bits
8 bits
NUMBER OF
STOP BITS
1
1.5
2
2
2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to
generate an even or odd number of 1s when the data word bits and the parity bit are summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic
"1" an even number of bits is transmitted and checked.
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