LPC47U33X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U33X

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

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(a) The host drives the nLFRAME signal

high, tristates the LAD[3:0] signals,

and ignores the nLDRQ signal.

(b) The LPC47U33x ignores nLFRAME,

tristates the LAD[3:0] pins and drives

the nLDRQ signal inactive (high).

LPC Transfers

Wait State Requirements

I/O Transfers

The LPC47U33x inserts three wait states for an

I/O read and two wait states for an I/O write

cycle. A SYNC of 0110 is used for all I/O

transfers. The exception to this is for transfers

where IOCHRDY would normally be deasserted

in an ISA transfer (i.e., EPP or IrCC transfers) in

which case the sync pattern of 0110 is used and

a large number of syncs may be inserted (up to

330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47U33x inserts three wait states for a

DMA read and four wait states for a DMA write

cycle. A SYNC of 0101 is used for all DMA

transfers.

See the example timing for the LPC cycles in

the “Timing Diagrams” section.

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