LPC47U33X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U33X

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

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PS/2 Mode

7

1

RESET 1

COND.

6

5

4

3

2

1

0

1 DRIVE WDATA RDATA WGATE MOT MOT

SEL0 TOGGLE TOGGLE

EN1 EN0

1

0

0

0

0

0

0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a

hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

7

6

nDRV2 nDS1

RESET N/A

1

COND.

5

nDS0

1

4

WDATA

F/F

0

3

RDATA

F/F

0

2

WGATE

F/F

0

1

nDS3

1

0

nDS2

1

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported in the LPC47U33x.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported in the LPC47U33x.

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