LPC47U33X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U33X

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

Prev 21 22 23 24 25 26 27 28 29 30 Next

BIT 3 DMAEN

PC/AT and Model 30 Mode:

Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will

disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset this bit

will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go

active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go

active.

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the LPC47U33x.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the LPC47U33x.

DRIVE

0

1

DOR VALUE

1CH

2DH

Tape Drive Register (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to

assign tape support to a particular drive during initialization. Any future references to that drive

automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive

number. Table 6 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and

cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated

when read. The TDR is unaffected by a software reset.

TAPE SEL1

(TDR.1)

0

0

1

1

Table 6 - Tape Select Bits

TAPE SEL0

(TDR.0)

DRIVE SELECTED

0

None

1

1

0

2

1

3

28

Share Link: