LPC61W492QFP View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC61W492QFP

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

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Register Descriptions

There are several status, data, and control registers in LPC61W492. These registers are defined

below:

ADDRESS

REGISTER

OFFSET

READ

WRITE

base address + 0

SA REGISTER

base address + 1

SB REGISTER

base address + 2

DO REGISTER

base address + 3

TD REGISTER

TD REGISTER

base address + 4

MS REGISTER

DR REGISTER

base address + 5

DT (FIFO) REGISTER

DT (FIFO) REGISTER

base address + 7

DI REGISTER

CC REGISTER

Status Register A (SA Register) (Read base address + 0)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,

the bit definitions for this register are as follows:

765 43 21 0

INIT PENDING (Bit 7):

This bit indicates the value of the floppy disk interrupt output.

nDRV2 (Bit 6):

0

A second drive has been installed

1

A second drive has not been installed

STEP (Bit 5):

This bit indicates the complement of nSTEP output.

nTRAK0 (Bit 4):

This bit indicates the value of nTRAK0 input.

DIR

nWP

nINDEX

HEAD

nTRAK0

STEP

nDRV2

INIT PENDING

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