LPC61W492QFP View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC61W492QFP

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

Prev 31 32 33 34 35 36 37 38 39 40 Next

nHEAD (Bit 3):

This bit indicates the value of nHEAD output.

0

side 1

1

side 0

INDEX (Bit 2):

This bit indicates the complement of nINDEX output.

WP (Bit 1):

0

disk is not write-protected

1

disk is write-protected

nDIR (Bit 0)

This bit indicates the direction of head movement.

0

inward direction

1

outward direction

Status Register B (SB Register) (Read base address + 1)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,

the bit definitions for this register are as follows:

7 6 5 4 3 21 0

11

MOT EN A

MOT EN B

WE

RDATA Toggle

WDATA Toggle

Drive SEL0

Drive SEL0 (Bit 5):

This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).

WDATA Toggle (Bit 4):

This bit changes state at every rising edge of the nWD output pin.

RDATA Toggle (Bit 3):

This bit changes state at every rising edge of the nRDATA output pin.

WE (Bit 2):

This bit indicates the complement of the nWE output pin.

MOT EN B (Bit 1)

This bit indicates the complement of the nMOB output pin.

MOT EN A (Bit 0)

This bit indicates the complement of the nMOA output pin.

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

36

Share Link: