LPC61W492QFP View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC61W492QFP

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

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Digital Output Register (DO Register) (Write base address + 2)

The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ

enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are

as follows:

7 6 5 4 3 2 1-0

Drive Select: 00 select drive A

01 select drive B

10 select drive C

11 select drive D

Floppy Disk Controller Reset

Active low resets FDC

DMA and INT Enable

Active high enable DRQ/IRQ

Motor Enable A. Motor A on when active high

Motor Enable B. Motor B on when active high

Motor Enable C. Motor C on when active high

Motor Enable D. Motor D on when active high

Tape Drive Register (TD Register) (Read base address + 3)

This register is used to assign a particular drive number to the tape drive support mode of the data

separator. This register also holds the media ID, drive type, and floppy boot drive information of the

floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are

as follows:

7 6 5 4 3 21 0

XX XX X X

Tape sel 0

Tape sel 1

If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:

765 43 21 0

Tape Sel 0

Tape Sel 1

Floppy boot drive 0

Floppy boot drive 1

Drive type ID0

Drive type ID1

Media ID0

Media ID1

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