LTC5599IUFPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5599IUFPBF' PDF : 42 Pages View PDF
LTC5599
Applications Information
I/Q DC Offset Adjustment (Registers 0x02 and 0x03)
and LO Leakage
Offsets in the I- and Q-channel translates into LO leakage
at the RF port. This offset can either be caused by the
I/Q modulator or, in case the baseband connections are
DC-coupled, applied externally. Registers 0x02 and 0x03
(I-offset and Q-offset) can be set to cancel this offset
and hence lower the LO leakage. To adjust the offset in
the I-channel, the BBPI DAC is set to a (slightly) different
value than the BBMI DAC, introducing an offset. These
8-bit registers defaults are 128 and represents 0 offset.
The register value can be set from 1 to 255. The value 0
represents an unsupported code and should not be used.
Since the input referred offset depends on the gain the
input offset value (VOS) can be calculated as:
VOS = 1260/((3632 • G)/(NOS – 128) – (NOS – 128)
/(3632 • G))
and Vos = 0 for Nos =128. G represents the gain from Table 3.
Table 3. Coarse Digital Gain (DG) Register Settings.
DG (dB)
G(V/V)
DEC
BINARY
HEX
0
1.000
0
00000
0x00
–1
0.891
1
00001
0x01
–2
0.794
2
00010
0x02
–3
0.708
3
00011
0x03
–4
0.631
4
00100
0x04
–5
0.562
5
00101
0x05
–6
0.501
6
00110
0x06
–7
0.447
7
00111
0x07
–8
0.398
8
01000
0x08
–9
0.355
9
01001
0x09
–10
0.316
10
01010
0x0A
–11
0.282
11
01011
0x0B
–12
0.251
12
01100
0x0C
–13
0.224
13
01101
0x0D
–14
0.200
14
01110
0x0E
–15
0.178
15
01111
0x0F
–16
0.158
16
10000
0x10
–17
0.141
17
10001
0x11
–18
0.126
18
10010
0x12
–19
0.112
19
10011
0x13
A positive offset means that the voltage of the positive
input terminal (BBPI or BBPQ) is increased relative to the
negative input terminal (BBMI or BBMQ).
I/Q Gain Ratio (Register 0x04) and Side-Band
Suppression
The 8-bit I/Q gain ratio register 0x04 controls the ratio of
the I-channel mixer conversion gain GI and the Q-channel
mixer conversion gain GQ. Together with the quadrature
phase imbalance register 0x05, register 0x04 allows further
optimization of the modulator side-band suppression.
The expression relating the gain ratio GI/GQ to the contents
of the 8-bit register 0x04, represented by decimal NIQ and
the nominal conversion gain G equals:
20 log (GI/GQ) = 20 log ((3632 • G – (NIQ – 128))/
(3632 • G +(NIQ –128))) (dB)
The step size of the gain ratio trim in dB vs NIQ is ap-
proximately constant for the same digital gain setting.
For digital gain setting = –4, for example, the step size
is about 7.6mdB. Table 4 lists the gain step size for each
digital gain setting that follows from the formula above.
Table 4. I/Q Gain Ratio Step Size vs Digital Gain
Setting
DG (dB)
0
G (V/V)
1.000
∆GI/GQ (mdB)
4.8
–1
0.891
5.4
–2
0.794
6.0
–3
0.708
6.8
–4
0.631
7.6
–5
0.562
8.5
–6
0.501
9.6
–7
0.447
10.7
–8
0.398
12.0
–9
0.355
13.5
–10
0.316
15.1
–11
0.282
17.1
–12
0.251
19.2
–13
0.224
21.5
–14
0.200
24.2
–15
0.178
27.3
5599f
22
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