LTC5599IUFPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5599IUFPBF' PDF : 42 Pages View PDF
LTC5599
Applications Information
specified register address. See Figure 8 for an example of a
detailed write sequence, and Figure 9 for a read sequence.
Figure 10 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register ad-
dress (Addr0) and an LSB of 0 indicating a write. The next
byte is the data intended for the register at address Addr0.
CSB is then taken high to terminate the transfer. The first
byte of the second burst contains the destination register
address (Addr1) and an LSB indicating a write. The next
byte on SDI is the data intended for the register at address
Addr1. CSB is then taken high to terminate the transfer.
Note that the written data is transferred to the internal
register at the falling edge of the 16th clock cycle (paral-
lel load).
MASTER–CSB
MASTER–SCLK
16 CLOCKS
7-BIT REGISTER ADDRESS
8 BITS OF DATA
PARALLEL LOAD
MASTER–SDI
LTC5599–SD0
A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 = WRITE
5599 F08
Figure 8. Serial Port Write Sequence
MASTER–CSB
MASTER–SCLK
16 CLOCKS
7-BIT REGISTER ADDRESS
MASTER–SDI A6 A5 A4 A3 A2 A1 A0 1
1 = READ
LTC5599–SDO
8 BITS OF DATA
X D7 D6 D5 D4 D3 D2 D1 D0 DX
5599 F09
Figure 9. Serial Port Read Sequence
MASTER–CSB
MASTER–SDI
ADDR0 + WR
BYTE 0
ADDR1 + WR
BYTE 1
LTC5599–SDO
5599 F10
Figure 10. Serial Port Single Byte Writes
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5599f
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