LTC5599IUFPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5599IUFPBF' PDF : 42 Pages View PDF
LTC5599
Applications Information
is recommended at these pins, forming a diplexer circuit
with center frequency of 200MHz. This diplexer helps to
improve the uncalibrated side-band suppression signifi-
cantly around 200MHz. Even for LO frequencies far from
200MHz the diplexer performs better than a single-ended
LO drive or a differential drive. Due to factory calibration
of the poly-phase filter the typical side-band suppression
is about 50dBc for frequencies from 100MHz to 700MHz
and 45dBc from 700MHz to 1300MHz. For narrow-band
applications far from 200MHz it may help to tune the
diplexer to a different frequency which can improve the
uncalibrated side-band suppression and the gain vs LO
drive level. The Typical Performance Characteristics section
shows the return loss for a 900MHz match (L1 = 8.2nH,
C5 = 3.3pF) and a 1260MHz match (L1 = 5.6nH, C5 = 3pF).
To get a performance with the standard 200MHz match
equivalent to the 900MHz and 1260MHz match, the LO
power should be increased by 1.5dB and 2dB respectively.
Register 0x00 values of Table 5 may have to be adjusted
as well, in case the standard match is not used.
Table 6 lists LOL and LOC port input impedance vs frequency
at EN = High and PLO = 0dBm. The other LO port (LOC or
LOL) is terminated in a 50Ω.
Table 6. LOL, LOC Port Input Impedance vs Frequency for EN
= High and PLO = 0dBm (Other LO Port Terminated with 50Ω to
Ground)
FREQ REG LOL/LOC PORT IMPEDANCE (W) REFL COEFFICIENT
(MHz) 0x00 REAL*
IMAG* (IND)
MAG ANGLE
20 79 7.9
24.3 (194nH)
0.750 175
30 79 9.1
19.0 (101nH)
0.743 172
40 79 10.8
17.4 (69nH)
0.732 169
50 79 13.0
17.6 (56nH)
0.716 165
60 79 15.7
18.9 (50nH)
0.693 162
70 79 18.6
21.4 (49nH))
0.661 158
80 79 21.6
25.0 (50nH)
0.618 154
90 79 24.4
30.3 (54nH)
0.564 151
100 75 27.0
38.3 (61nH))
0.497 148
110 70 29.0
51.4 (74nH)
0.419 146
120 6C 30.3
76.1 (101nH)
0.338 149
130 68 32.3
109.3 (134nH)
0.276 150
LOL
3
140 64 34.3
150 62 36.2
121.6 (138nH)
119.4 (127nH)
0.247 148
0.234 142
LOC
4
160 5E 37.4
170 5C 37.1
149.1 (148nH))
357.5 (335nH)
0.201 143
0.160 162
180 59 39.6
188.6 (167nH)
0.164 141
190 57 41.4
192.0 (161nH))
0.150 135
5599 F02
Figure 2. Simplified Circuit Schematic for the LOL and LOC Inputs
Below 100MHz the matching network of Figure 3 can be
used.The side-band suppression in that case is largely
defined by the diplexer L1, C5 and the (temperature de-
pendent) LOL and LOC input impedance. See measured
performance in the Typical Performance Characteristics
section.
30MHz/70MHz
L2
120nH/51nH
LO
C19
180pF/47pF
L1
47nH/43nH
C5
560pF/120pF
3 LOL
C20
270pF/100pF
4 LOC
C21
270pF/100pF
5599 F03
Figure 3. Impedance Matching Network for LOL and LOC
Interfaces Matched at 30MHz/70MHz
200 54 40.7
*Parallel Equivalent
418.6 (333nH)
0.116 156
The circuit schematic of the demo board is shown in
Figure 13.
I/Q Phase Balance Adjustment Register 0x05 and
Side-Band Suppression
Ideally the I-channel LO phase is exactly 90° ahead of the
Q-channel LO phase, so called quadrature. In practice how-
ever, the I/Q phase difference differs from exact quadrature
by a small error due to component parameter variations
and harmonic content in the LO signal (see below).
The I/Q phase imbalance register (0x05) allows adjust-
ment of the I/Q phase shift to compensate for such errors.
Together with gain ratio register 0x04, it can thus be used
to optimize the side-band suppression of the modulator.
5599f
For more information www.linear.com/LTC5599
25
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