M24C02-DRMF3G View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M24C02-DRMF3G

Automotive 2-Kbit serial I²C bus EEPROM with 1 MHz clock

STMicroelectronics 

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Instructions

M24C02-A125

4.2

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device internal address counter is

incremented by one, to point to the next byte address.

Figure 8. Read mode sequences

#URRENT

!DDRESS

2EAD

!#+

./!#+

$EVSELECT

$ATAOUT

27

2ANDOM

!DDRESS

2EAD

!#+

!#+

!#+

./!#+

$EVSELECT

"YTEADDRESS

$EVSELECT

$ATAOUT

27

27

4.2.1

3EQUENTIAL

#URRENT

2EAD

!#+

!#+

$EVSELECT

$ATAOUT

27

!#+

./!#+

$ATAOUT.

3EQUENTIAL

2ANDOM

2EAD

!#+

!#+

!#+

!#+

$EVSELECT

"YTEADDRESS

$EVSELECT

$ATAOUT

27

27

!#+

./!#+

$ATAOUT.

!)B

Random Address Read

The Random Address Read is a sequence composed of a truncated Write sequence (to

define a new address pointer value, see Table 3) followed by a current Read.

The Random Address Read sequence is therefore the sum of [Start + Device Select code

with R/W=0 + address byte] (without Stop condition, as shown in Figure 8) and [Start

condition + Device Select code with R/W=1]. The memory device acknowledges the

sequence and then outputs the contents of the addressed byte. To terminate the data

transfer, the bus master does not acknowledge the last data byte and then issues a Stop

condition.

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DocID025755 Rev 5

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