M41ST87Y, M41ST87W
Table 13. Default Values
Condition
TR
ST
OF
OFIE
HT(3)
Out
FT
AFE
Initial Power-up
0
0
1
0
1
1
0
0
Subsequent Power-up (with
battery back-up)(1,2)
UC
UC
UC
0⇑
1⇓
UC
0⇓
0⇑
Condition
Initial Power-up
Subsequent Power-up (with
battery back-up)(1,2)
ABE
0
0⇑
SQWE
0
0⇑
SQWOD
1
UC
PFOD
1
UC
WATCHDOG Register(4)
0
0⇓
Condition
Initial Power-up
Subsequent Power-up (with
battery back-up)(1)
32kE
1(5)
UC
THS
0
UC
TEB1 and 2 TCM1 and 2 TPM1 and 2 TDS1 and 2
0
0
0
0
UC
UC
UC
UC
Condition
TCHI/TCLO1
and 2
CLR1 and 2
TIE1 and 2
CLRPW0
CLRPW1
Initial Power-up
0
0
0
0
0
Subsequent Power-up (with
battery back-up)(1)
UC
UC
0⇑
UC
UC
Note: All other control bits are undetermined.
Note: 1. UC = Unchanged.
2. ⇑ = VCC rising; ⇓ = VCC falling.
3. When TEBX is set to '1,' the HT Bit will not be set on power-down (Tamper Time-Stamp will have precedence).
4. WDS, BMB0-BMB4, RB0, RB1.
5. 32kHz output valid only on VCC.
CLR1EXT
and
CLR2EXT
0
UC
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