M95256-CS3G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95256-CS3G' PDF : 48 Pages View PDF
M95256-DR, M95256, M95256-W, M95256-R
DC and AC parameters
Table 18. AC characteristics, new M95256-W, device grade 6
Test conditions: VCC = 2.5 to 5.5 V,
TA = -40 to 85 °C
New products (process K,
CL = 100 pF preliminary information)
CL = 30 pF
Unit
Symbol Alt.
Parameter
Min. Max. Min. Max. Min. Max.
fC
fSCK Clock frequency
D.C. 5 D.C. 10 D.C. 20 MHz
tSLCH
tCSS1 S active setup time
90
30
15
ns
tSHCH
tCSS2 S not active setup time
90
30
15
ns
tSHSL
tCS
S deselect time
100
40
20
ns
tCHSH
tCSH S active hold time
90
30
15
ns
tCHSL
S not active hold time
90
30
15
ns
tCH (1)
tCLH Clock high time
90
45
20
ns
tCL (1)
tCLL Clock low time
90
45
20
ns
tCLCH (2) tRC
Clock rise time
1
2
2
µs
tCHCL (2) tFC
Clock fall time
1
2
2
µs
tDVCH
tDSU Data in setup time
20
10
5
ns
tCHDX
tDH
Data in hold time
30
10
10
ns
tHHCH
Clock low hold time after HOLD not
70
30
15
ns
active
tHLCH
Clock low hold time after HOLD active
40
30
15
ns
tCLHL
Clock low setup time before HOLD active 0
0
0
ns
tCLHH
Clock low setup time before HOLD not
0
0
0
ns
active
tSHQZ (2) tDIS
Output disable time
100
40
20 ns
tCLQV
tV
Clock low to output valid
60
40
20 ns
tCLQX
tHO
Output hold time
0
0
0
ns
tQLQH (2) tRO
Output rise time
50
40
20 ns
tQHQL (2) tFO
Output fall time
50
40
20 ns
tHHQV
tLZ
HOLD high to output valid
50
40
20 ns
tHLQZ (2) tHZ
HOLD low to output High-Z
100
40
20 ns
tW
tWC Write time
5
5
5 ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not tested in production.
Doc ID 12276 Rev 11
35/48
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