M95320-W View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95320-W' PDF : 48 Pages View PDF
DC and AC parameters
M95320-W M95320-R M95320-DR
Table 17. AC characteristics (M95320-W, device grade 6)
Test conditions specified in Table 10 and Table 11
Min. Max. Min. Max.
Symbol Alt.
Parameter
New products Unit
VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V
fC
fSCK Clock frequency
D.C.
10
D.C.
20 MHz
tSLCH tCSS1 S active setup time
30
15
ns
tSHCH tCSS2 S not active setup time
30
15
ns
tSHSL
tCS S deselect time
40
20
ns
tCHSH tCSH S active hold time
30
15
ns
tCHSL
tCH(1)
tCL(1)
tCLCH(2)
tCHCL(2)
S not active hold time
tCLH Clock high time
tCLL Clock low time
tRC Clock rise time
tFC Clock fall time
30
15
ns
42
20
ns
40
20
ns
2
2
µs
2
2
µs
tDVCH tDSU Data in setup time
10
5
ns
tCHDX
tDH Data in hold time
10
10
ns
tHHCH
Clock low hold time after HOLD not active
30
15
ns
tHLCH
Clock low hold time after HOLD active
30
15
ns
tCLHL
Clock low set-up time before HOLD active
0
0
ns
tCLHH
Clock low set-up time before HOLD not active 0
0
ns
tSHQZ(2) tDIS Output disable time
40
20
ns
tCLQV(3)
tV Clock low to output valid
40
20
ns
tCLQX
tQLQH(2)
tQHQL(2)
tHO Output hold time
tRO Output rise time
tFO Output fall time
0
0
ns
40
20
ns
40
20
ns
tHHQV
tHLQZ(2)
tLZ HOLD high to output valid
tHZ HOLD low to output high-Z
40
20
ns
40
20
ns
tW
tWC Write time
5
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
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Doc ID 5711 Rev 14
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