LAPIS Semiconductor
FEDL9092-01
ML9092-01/02/03/04
Clock Synchronous Serial Transfer Example (WRITE)
Transfer start
CS
Transfer complete
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CP
DI/O
“1” “1” R/W D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Register bits
Instruction code
Data
Clock Synchronous Serial Continuous Data Transfer Example (WRITE: Example of display data RAM
write)
Transfer start
CS
Transfer complete
*1
1 2 7 8 9 10 15 16 17 18 23 24 41 42 47 48
CP
DI/O
Instruction code
Data 1
Data 2
Data 5
*1: Be sure to write data in 8 bits. If the CS signal falls when data input operation in 8 bits is not
complete, the last 8-bit data write is invalid. (The previously written data is valid.)
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