ML9092-02 View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9092-02' PDF : 66 Pages View PDF
LAPIS Semiconductor
FEDL9092-01
ML9092-01/02/03/04
Output Pin, I/O Pin and Register States When Reset Is Input
Pin and register states while the RESET input is pulled to a “L” level are listed below.
Output pin, I/O pin
DI/O
KREQ
OSC2
R0/C0 to R4/C4 (when these pins are used for key
scanning in ML9092-01);
R0 to R5 (ML9092-02/03);
R0 toR4 (ML9092-04)
R0/C0 to R4/C4 (when these pins are used as port C
outputs in ML9092-01)
C0/D0 to C4/D4 (when these pins are used as port D
outputs in ML9092-01)
PA0
PB0 to PB2 (ML9092-01/04)
SEG1 to SEG56 (ML9092-01);
SEG1 to SEG60 (ML9092-02/03/04)
COM1 to COM10
Input state
“L” (VSS)
Oscillating state
“L” (VSS)
State
High impedance
High impedance (any pull-up resistors are turned off)
High impedance
High impedance
VSS
VSS
Register
Key scan register
Display data register
X address register
Y address register
Port A register
Port B register (ML9092-01/04)
Port C register
(When KPS = “0” in ML9092-01)
Port D register
(When KPS = “0” in ML9092-01)
Control register 1
Control register 2
Rotary encoder read register
Contrast ADJ register
PWM0 register (for ML9092-01/04)
PWM1 register (for ML9092-01/04)
PWM2 register (for ML9092-01/04)
State
Reset to “0”
Display data is retained
Reset to “0”
Reset to “0”
Reset to “0”
Reset to “0”
Reset to “0”
Reset to “0”
Bits INC and KT are set to “1”.
Bits WLS, SHL, PE, DTY1 and DTY0 are reset to “0”.
Display OFF, normal mode
(Standby mode is released)
Reset to “0”
Set to “F”
Reset to “0”
Reset to “0”
Reset to “0”
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