MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 78 Pages View PDF
1.3.16 PSC
1.3.16.1 Codec Mode (8-,16-, 24-, and 32-bit)/I2S Mode
Table 42. Timing Specifications—8-, 16-, 24-, and 32-bit CODEC / I2S Master Mode
Sym
Description
Min
Typ
Max Units SpecID
1
Bit Clock cycle time, programmed in CCS register
40.0
—
2
Clock duty cycle
—
50
3
Bit Clock fall time
—
—
4
Bit Clock rise time
—
—
5
FrameSync valid after clock edge
—
—
6
FrameSync invalid after clock edge
—
—
7
Output Data valid after clock edge
—
—
8
1 Bit Clock cycle time.
Input Data setup time
6.0
—
—
ns A15.1
—
%(1) A15.2
7.9
ns A15.3
7.9
ns A15.4
8.4
ns A15.5
8.4
ns A15.6
9.3
ns A15.7
—
ns A15.8
NOTE
Output timing is specified at a nominal 50 pF load.
1
BitClk
( CLKPOL = 0 )
Output
BitClk
( CLKPOL = 1 )
Output
2
2
5
3
4
4
3
FrameSync
(SyncPol = 1)
Output
6
FrameSync
(SyncPol = 0)
Output
7
TxD
Output
8
RxD
Input
Figure 37. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I2S Master Mode
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
47
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