MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 78 Pages View PDF
IrDA_TX
(SIR / FIR / MIR)
1
2
3
4
Figure 40. Timing Diagram — IrDA Transmit Line
1.3.16.4 SPI Mode
Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym
Description
Min
1
SCK cycle time, programable in the PSC CCS register
30.0
2
SCK pulse width, 50% SCK duty cycle
15.0
3
Slave select clock delay, programable in the PSC CCS register 30.0
4
Output Data valid after Slave Select (SS)
—
5
Output Data valid after SCK
—
6
Input Data setup time
6.0
7
Input Data hold time
1.0
8
Slave disable lag time
—
9 Sequential Transfer delay, programable in the PSC CTUR / CTLR 15.0
register
10
Clock falling time
—
11
Clock rising time
—
Max Units SpecID
—
ns A15.26
—
ns A15.27
—
ns A15.28
8.9
ns A15.29
8.9
ns A15.30
—
ns A15.31
—
ns A15.32
8.9
ns A15.33
—
ns A15.34
7.9
ns A15.35
7.9
ns A15.36
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
50
Freescale Semiconductor
Share Link: 
