1.3.16.2 AC97 Mode
Table 44. Timing Specifications — AC97 Mode
Sym
Description
Min
Typ
Max Units SpecID
1
Bit Clock cycle time
—
81.4
—
ns A15.15
2
Clock pulse high time
—
40.7
—
ns A15.16
3
Clock pulse low time
—
40.7
—
ns A15.17
4
FrameSync valid after rising clock edge
—
—
13.0
ns A15.18
5
Output Data valid after rising clock edge
—
—
14.0
ns A15.19
6
Input Data setup time
1.0
—
—
ns A15.20
7
Input Data hold time
1.0
—
—
ns A15.21
NOTE
Output timing is specified at a nominal 50 pF load.
1
BitClk
( CLKPOL = 0 )
Input
4
3
2
FrameSync
(SyncPol = 1)
Output
Sdata_out
Output
Sdata_in
Input
5
6
7
Figure 39. Timing Diagram — AC97 Mode
1.3.16.3 IrDA Mode
Table 45. Timing Specifications — IrDA Transmit Line
Sym
1
2
3
4
Description
Pulse high time, defined in the IrDA protocol definition
Pulse low time, defined in the IrDA protocol definition
Transmitter rising time
Transmitter falling time
Min
0.125
0.125
—
—
Max
10000
10000
7.9
7.9
Units SpecID
μs A15.22
μs A15.23
ns A15.24
ns A15.25
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
49