MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
1
SCK
( CLKPOL = 0 )
Input
SCK
( CLKPOL = 1 )
Input
SS
Input
2
2
3
8
9
6
7
MOSI
Input
4
5
MISO
Output
Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
1
Cycle time
4
1024
2
Clock high or low time
2
512
3
Slave select to clock delay
15.0
—
4
Output data valid
—
20.0
5
Input Data setup time
20.0
—
6
Input Data hold time
20.0
—
7
Slave disable lag time
15.0
—
8
Sequential Transfer delay
1
—
9
Clock falling time
—
7.9
10
Clock rising time
—
7.9
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Units
SpecID
IP-Bus Cycle(1) A11.21
IP-Bus Cycle(1) A11.22
ns
A11.23
ns
A11.24
ns
A11.25
ns
A11.26
ns
A11.27
IP-Bus Cycle(1) A11.28
ns
A11.29
ns
A11.30
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
43
Share Link: 
