MPC5200B View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC5200B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

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Table 43. Timing Specifications — 8-, 16-, 24-, and 32-bit CODEC / I2S Slave Mode

Sym

Description

1

Bit Clock cycle time

2

Clock duty cycle

3

FrameSync setup time

4

Output Data valid after clock edge

5

Input Data setup time

6

Input Data hold time

1 Bit Clock cycle time.

Min

Typ

Max Units SpecID

40.0

—

—

50

—

ns A15.9

—

%(1) A15.10

1.0

—

—

ns A15.11

—

—

14.0

ns A15.12

1.0

—

—

ns A15.13

1.0

—

—

ns A15.14

NOTE

Output timing is specified at a nominal 50 pF load.

1

BitClk

( CLKPOL = 0 )

Input

BitClk

( CLKPOL = 1 )

Input

2

2

3

FrameSync

(SyncPol = 1)

Input

FrameSync

(SyncPol = 0)

Input

4

TxD

Output

5

RxD

Input

6

Figure 38. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I2S Slave Mode

MPC5200B Data Sheet, Rev. 4

48

Freescale Semiconductor

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