MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
Table 41. I2C Output Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1 (1)
Start condition hold time
6
2( 1)
Clock low time
10
3(2)
SCL/SDA rise time
—
4(1)
Data hold time
7
5(1)
SCL/SDA fall time
—
6(1)
Clock high time
10
7(1)
Data setup time
2
8(1) Start condition setup time (for repeated start condition
20
only )
9(1)
Stop condition setup time
10
— IP-Bus Cycle(3) A13.8
— IP-Bus Cycle(3) A13.9
7.9
ns
A13.10
— IP-Bus Cycle(3) A13.11
7.9
ns
A13.12
— IP-Bus Cycle(3) A13.13
— IP-Bus Cycle(3) A13.14
— IP-Bus Cycle(3) A13.15
— IP-Bus Cycle(3) A13.16
1 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
3 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
NOTE
Output timing is specified at a nominal 50 pF load.
2
6
5
SCL
1
4
7
8
3
9
SDA
Figure 36. Timing Diagram—I2C Input/Output
1.3.15 J1850
See the MPC5200B User’s Manual (MPC5200BUM).
MPC5200B Data Sheet, Rev. 4
46
Freescale Semiconductor
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