MPC5644B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5644B' PDF : 114 Pages View PDF
9 This value is obtained from limited sample set
10 Subject to change, Configuration: 1 e200z4d + 4 kbit/s Cache, 1 e200z0h (1/2 system frequency), CSE,
1 eDMA (10 ch.), 6 FlexCAN (4 500 kbit/s, 2 125 kbit/s), 4 LINFlexD (20 kbit/s), 6 DSPI (2 2 Mbit/s,
3 4 Mbit/s, 1 10 Mbit/s), 16 Timed I/O, 16 ADC Input, 1 FlexRay (2 ch., 10 Mbit/s), 1 FEC (100 Mbit/s),
1 RTC, 4 PIT, 1 SWT, 1 STM. For lower pin count packages reduce the amount of timed I/O’s and ADC
channels. RUN current measured with typical application with accesses on both code flash and RAM.
11 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:
instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0
ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance:
0 (clocked but no communication, instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no
conversion except 2 analog watchdogs.
12 Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON.
All possible peripherals off and clock gated. Flash in power down mode.
13 This current is the maximum value at room temperature for any sample. The condition is same as note 11.
14 Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum
consumption, all possible modules switched-off.
15 Only for the “P” classification: LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum
consumption, all possible modules switched-off.
16 LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules
switched OFF.
4.10 Flash memory electrical characteristics
4.10.1 Program/Erase characteristics
Table 25 shows the code flash memory program and erase characteristics.
Table 25. Code flash memory—Program and erase specifications
Value
Symbol C
Parameter
Min
Typ1
Initial
max2
Unit
Max3
Tdwprogram
Double word (64 bits) program time4
—
18
50
500 µs
T16Kpperase
C 16 KB block pre-program and erase time
—
T32Kpperase
32 KB block pre-program and erase time
—
200
500
5000 ms
300
600
5000 ms
T128Kpperase
128 KB block pre-program and erase time
—
Teslat CC D Erase Suspend Latency
—
600
1300
5000 ms
—
30
30
µs
tESRT
C Erase Suspend Request Rate
20
—
—
—
ms
tPABT
D Program Abort Latency
—
—
10
10
µs
tEAPT
D Erase Abort Latency
—
—
30
30
µs
1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
MPC5646C Microcontroller Data Sheet, Rev. 3
60
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Share Link: 
