MPC8349VVAGDB View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8349VVAGDB
Freescale Semiconductor
'MPC8349VVAGDB' PDF : 87 Pages View PDF
RESET Initialization
4.3 TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit Notes
EC_GTX_CLK125 frequency
tG125
—
EC_GTX_CLK125 cycle time
tG125
—
EC_GTX_CLK125 rise and fall time
tG125R/tG125F
—
LVDD = 2.5 V
LVDD = 3.3 V
EC_GTX_CLK125 duty cycle
tG125H/tG125
GMII, TBI
45
1000Base-T for RGMII, RTBI
47
125
—
MHz
—
8
—
ns
—
—
ns
1
0.75
1.0
—
%
2
55
53
EC_GTX_CLK125 jitter
—
—
—
±150
ps
2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349EA.
5.1 RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA.
Table 9. RESET Pins DC Electrical Characteristics1
Parameter
Input high voltage
Input low voltage
Input current
Output high voltage2
Output low voltage
Symbol
VIH
VIL
IIN
VOH
VOL
Condition
—
—
—
IOH = –8.0 mA
IOL = 8.0 mA
Min
2.0
–0.3
—
2.4
—
Max
Unit
OVDD + 0.3
V
0.8
V
±5
μA
—
V
0.5
V
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
13
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