MPC8349VVAGDB View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGDB

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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Figure 7 shows the DDR SDRAM output timing diagram.

MCK[n]

MCK[n]

tMCK

DUART

ADDR/CMD/MODT

tDDKHAS, tDDKHCS

tDDKHAX, tDDKHCX

Write A0

NOOP

tDDKHMP

tDDKHMH

MDQS[n]

MDQ[x]

tDDKHDS

tDDKLDS

D0

D1

tDDKHDX

tDDKLDX

Figure 7. DDR SDRAM Output Timing Diagram

Figure 8 provides the AC test load for the DDR bus.

Output

Z0 = 50 Ω

RL = 50 Ω

GVDD/2

tDDKHME

Figure 8. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8349EA.

7.1 DUART DC Electrical Characteristics

Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8349EA.

Table 21. DUART DC Electrical Characteristics

Parameter

High-level input voltage

Low-level input voltage

Input current (0.8 V ≤ VIN ≤ 2 V)

Symbol

VIH

VIL

IIN

Min

Max

Unit

2

–0.3

—

OVDD + 0.3

V

0.8

V

±5

μA

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

21

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