MPC8349VVAGDB View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGDB

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

Prev 21 22 23 24 25 26 27 28 29 30 Next

Ethernet: Three-Speed Ethernet, MII Management

Table 30. TBI Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising

PMA_RX_CLK

tTRDVKH2

2.5

—

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising

tTRDXKH2

1.5

—

PMA_RX_CLK

—

ns

—

ns

RX_CLK clock rise time (20%–80%)

tTRXR

0.7

—

2.4

ns

RX_CLK clock fall time (80%–20%)

tTRXF

0.7

—

2.4

ns

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing

(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to

the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol

is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI

(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For

symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).

2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times

of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.

Figure 15 shows the TBI receive AC timing diagram.

tTRX

tTRXR

PMA_RX_CLK1

tTRXH

tTRXF

RCG[9:0]

Even RCG Odd RCG

PMA_RX_CLK0

tTRDVKH

tSKTRX

tTRDXKH

tTRXH

tTRDXKH

tTRDVKH

Figure 15. TBI Receive AC Timing Diagram

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

29

Share Link: