MPC8349VVAGDB View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGDB

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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RESET Initialization

Table 9. RESET Pins DC Electrical Characteristics1 (continued)

Parameter

Symbol

Condition

Min

Output low voltage

VOL

IOL = 3.2 mA

—

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Max

Unit

0.4

V

5.2 RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8349EA.

Table 10. RESET Initialization Timing Specifications

Parameter

Min

Max

Unit Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

32

Required assertion time of PORESET with stable clock applied to CLKIN when the 32

MPC8349EA is in PCI host mode

—

tPCI_SYNC_IN 1

—

tCLKIN

2

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN

32

when the MPC8349EA is in PCI agent mode

—

tPCI_SYNC_IN 1

HRESET/SRESET assertion (output)

512

HRESET negation to SRESET negation (output)

16

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

4

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is

in PCI host mode

—

tPCI_SYNC_IN 1

—

tPCI_SYNC_IN 1

—

tCLKIN

2

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

4

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is

in PCI agent mode

—

tPCI_SYNC_IN 1

Input hold time for POR configuration signals with respect to negation of HRESET

0

—

ns

—

Time for the MPC8349EA to turn off POR configuration signals with respect to the

—

4

assertion of HRESET

ns

3

Time for the MPC8349EA to turn on POR configuration signals with respect to the

1

negation of HRESET

—

tPCI_SYNC_IN 1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied

to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

14

Freescale Semiconductor

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