DDR and DDR2 SDRAM
6.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
Min
Max
Unit Notes
ADDR/CMD/MODT output setup with respect to MCK
400 MHz
tDDKHAS
1.95
ns
3
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
ADDR/CMD/MODT output hold with respect to MCK
400 MHz
tDDKHAX
1.95
ns
3
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MCS(n) output setup with respect to MCK
400 MHz
tDDKHCS
1.95
ns
3
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MCS(n) output hold with respect to MCK
400 MHz
tDDKHCX
1.95
ns
3
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MCK to MDQS Skew
MDQ/MECC/MDM output setup with respect to
MDQS
400 MHz
tDDKHMH
tDDKHDS,
tDDKLDS
–0.6
700
0.6
ns
4
ps
5
—
333 MHz
775
—
266 MHz
1100
—
200 MHz
1200
—
MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX,
tDDKLDX
400 MHz
700
ps
5
—
333 MHz
900
—
266 MHz
1100
—
200 MHz
1200
—
MDQS preamble start
tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK + 0.6 ns
6
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
19