MSM514252A-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514252A-10JS' PDF : 33 Pages View PDF
¡ Semiconductor
MSM514252A
PIN FUNCTION
Address Input: A0 - A8
The 18 address bits decode an 8-bit location out of the 262,144 locations in the MSM514252A
memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard
DRAM. Nine row address bits are latched at the falling edge of RAS. The following nine column
address bits are latched at the falling edge of CAS.
Row Addres Strobe: RAS
RAS is a basic RAM control input signal. The RAM port is in standby mode when the RAS level
is "high". As the standard DRAM’s RAS signal function, RAS is the control input that latches the
row address bits and a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAM signal functions, the level of the input signals, CAS, DT/
OE, WB/WE, and SE, at the falling edge of RAS, determines the MSM514252A operation modes.
Column Address Strobe: CAS
As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the
column address input and acts as an RAM port output enable signal.
Data Transfer/Output Enable: DT/OE
DT/OE is also a control input signal having multiple functions. As the standard DRAM’s OE
signal function, DT/OE is used as an output enable control when DT/OE is "high" at the falling
edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when the DT/OE is "low" at the falling edge of RAS.
Write per Bit/Write Enable: WB/WE
WB/WE is a control input signal having multiple functions. As the standard DRAM’s WE signal
function, it is used to write data into the memory array on the RAM port when WB/WE is "high"
at the falling edge of RAS.
In addition to the conventional WE signal function, the WB/WE determines the write-per-bit
function when WB/WE is "low" at the falling edge of RAS, during RAM port operations. The
WB/WE also determines the direction of data transfer between the RAM and SAM. When WB/
WE is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (read transfer).
When WB/WE is "low" at the falling edge of RAS, the data is transferred from SAM to RAM
(write transfer).
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