MSM514252A-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514252A-10JS' PDF : 33 Pages View PDF
¡ Semiconductor
MSM514252A
Write Transfer Cycle
A write transfer cycle transfers the contents of the SAM register into a selected row of the RAM
array. If the SAM data to be transferred must first be loaded through the SAM port, a pseudo
write transfer operation must precede the write transfer cycles.
However, if the SAM data to be transferred into the RAM was previously loaded into the SAM
via a read transfer, the SAM to RAM transfer can be executed simply by performing a write
transfer cycle.
A write transfer is invoked by holding CAS "low", WB/WE "low" and SE "low" at the falling edge
of RAS.
The row address selected at the falling edge of RAS determines the RAM row address into which
the data will be transferred. The column address selected at the falling edge of CAS determines
the start address of the serial pointer of the SAM.
After the write transfer is completed, the SIO lines are set in the input mode so that serial data
synchronized with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the RAS cycle of the preceding write transfer is completed.
Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising
edge of the SC clock is only allowed after the specified delay tSRD from the rising edge of RAS,
at which time a new row of data can be written in the serial register.
Pseudo Write Transfer Cycle
A pseudo write transfer cycle must be performed before loading data into the serial register after
a read transfer operation has been executed. The only purpose of a pseudo write transfer is to
change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM
does not occur).
After the serial register is loaded with new data, a write transfer cycle must be performed to
transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding CAS "high"
DT/OE "low", WB/WE "low" and SE "high" at the falling edge of RAS. The timing conditions
are the same as the one for the write transfer cycle except for the state of SE at the falling edge
of RAS.
Transfer Operation Without CAS
During all transfer cycles, the CAS input clock must be cycled, so that the column addresses are
latched at the falling edge of CAS, to set the SAM tap location. If CAS was maintained at a
constant "high" level during a transfer cycle, the SAM pointer location would be undefined.
Therefore a transfer cycle with CAS held "high" is not allowed.
Normal Read Transfer Cycle After Normal Read Transfer Cycle
Another read transfer may be performed following the read transfer provided that a minimum
delay of 30 ns from the rising edge of the first clock SC is satisfied.
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