MSM514252A-10JS View Datasheet(PDF) - Oki Electric Industry
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MFG CO.
'MSM514252A-10JS' PDF : 33 Pages View PDF
¡ Semiconductor
MSM514252A
DATA TRANSFER OPERATION
The MSM514252A features an internal data transfer capability between RAM and the SAM.
During a transfer cycle, 512 words by 4 bits of data can be loaded from RAM to SAM (Read
Transfer) or from SAM to RAM (Write Transfer).
The MSM514252A supports three types of transfer operations: Read transfer, Write Transfer and
pseudo write transfer. Data transfer operations between RAM and SAM are invoked by holding
the DT/OE signal "low" at the falling edge of RAS, the type of data transfer operation is
determined by the state of CAS, WB/WE and SE latched at the falling edge of RAS.
During data transfer operations, the SAM port is switched from input to output mode (Read
transfer) or output to input mode (Write transfer/pseudo write transfer).
During a data transfer cycle, the row A0-A8 select one of the 512 rows of the memory array to or
from which data will be transferred and the column address A0-A8 select one of the tap locations
in the serial register. The selected tap location is the start position in the SAM port from which
the first serial data will be read out during the subsequent serial read cycle or the start position
in the SAM port into which the first serial data will be written during the subsequent serial write
cycle.
Read Transfer Cycle
A read transfer consists of loading a selected row of data from the RAM array into the SAM
register. A read transfer is invoked by holding CAS "high", DT/OE "low" and WB/WE "high"
at the falling edge of RAS. The row address selected at the falling edge of RAS determines the
RAM row tho by transferred into the SAM.
The transfer cycle is completed at the rising edge of DT/OE. When the transfer is completed,
the SAM port is set into the output mode.
In a read/real time read transfer cycle, the transfer of a new row of data is completed at the rising
edge of DT/OE and this data becomes valid on the SIO lines after the specified access time tSCA
from the rising edge of the subsequent serial clock (SC) cycle. The start address of the serial
pointer of the SAM is determined by the column address selected at the falling edge of CAS.
In a read transfer cycle preceded by a write transfer cycle, the SC clock must be held at a constant
VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur
until after the specified delay tTSD from the rising edge of DT/OE.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SIO lines until the DT/OE signal goes "high" and the serial access time
tSCA for the following serial clock is satisfied.
This feature allows for the first bit of the new row of data to appear on the serial output as soon
as the last bit of the previous row has been strobed without any timing loss. To make this
continuous data flow possible , the rising edge of DT/OE must be synchronized with RAS, CAS
and the subsequent rising edge of SC (tRTH, tCTH, and tTSL/tTSD must be satisfied). The timing
restriction tTSL/tTSD are 5 ns min./10 ns min..
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