1Semiconductor
PEDL66577-01
MSM66577 Family
AC Characteristics 1 (VDD = 4.5 to 5.5 V)
(1) Separate Bus Type
External program memory control
Parameter
Cycle time
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
PSEN pulse width
PSEN pulse delay time
Address setup time
Address hold time
Instruction setup time
Instruction hold time
Read data access time
Symbol
tcyc
tφWH
tφWL
tPW
tPD
tAS
tAH
tIS
tIH
tACC
Condition
fOSC = 30 MHz
CL = 50 pF
tcyc
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Min.
Max.
Unit
33.3
—
13
—
13
—
2 tφ – 15
—
—
45
ns
tφ – 25
—
0
—
25
—
0
—
—
3 tφ – 65
Note: tφ = tcyc/2
CPUCLK
PSEN
A0 to A19
D0 to D7
tφWH
tφWL
tPD
tPW
PC0 to 19
tAS
tAH
INST0 to 7
tACC
tIS
tIH
Bus timing during no wait cycle time
14/34