1Semiconductor
PEDL66577-01
MSM66577 Family
(2) Multiplexed bus type
External program memory control
Parameter
Cycle time
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
PSEN pulse width
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
Symbol
tcyc
tφWH
tφWL
TAW
tPW
tPAD
tALS
tALH
tAHS
tAHH
tIS
tIH
Condition
fOSC = 30 MHz
CL = 50 pF
tcyc
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Min.
Max.
Unit
33.3
—
13
—
13
—
2 tφ – 10
—
2 tφ – 15
—
tφ – 3
—
ns
2tφ – 15
—
tφ – 3
—
3tφ – 25
—
0
—
25
—
0
tφ – 3
Note: tφ = tcyc/2
CPUCLK
ALE
PSEN
AD0 to AD7
A8 to A19
tφWH
tφWL
tAW
tPAD
PC0 to 7
tALS
tALH
PC8 to 19
tAHS
tPW
INST0 to 7
tIS
tIH
tAHH
Bus timing during no wait cycle time
16/34